CrashTest is a fast, high-fidelity, flexible resiliency analysis system. Starting from a hardware description model of the design under analysis, CrashTest is capable of orchestrating and performing a comprehensive design resiliency analysis by examining how the design reacts to faults while running software applications.
CrashTest provides a high-fidelity analysis report obtained by performing a fault injection campaign at the gate-level netlist of the design. The fault injection and analysis process is significantly accelerated by the use of an FPGA hardware emulation platform.
CrashTest is available out of the box for Leon3 and OpenSPARC T1 on the Xilinx University Program XUPV5-LX110T Development System
The current version of Crashtest has been tested on designs synthesized with the Synopsys GTECH library and supports the following fault models: bridge, path-delay, stuck-at, stuck-open, and transient.
CrashTest has been developed at the University of Michigan, Ann Arbor and it is publicly available under GPL license v2.0.
The basic version of CrashTest for Leon3 and OpenSPARC T1 consists of the following:
CrashTest can be customized to work with any design and technology library. Scripts to inject faults and projects to adapt Crashtest to any design and FPGA device are below: