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Electrical Stability of Advanced Amorphous Silicon Thin-Film Transistor for Flat Panel Displays

Alex Kuo and Jerzy Kanicki

Amorphous silicon thin-film-transistor (a-Si:H TFT) is used in active-matrix liquid-crystal display (AM-LCD) due to its low off current, and in active-matrix organic light-emitting display (AM-OLED) because of its fabrication versatility and reasonable device electrical performance.  However, joule heating from AM-LCD backlight or light-emitting device in AM-OLED can increase the internal temperature of the display, up to 80ºC in extreme cases.  Our objective was to evaluate the feasibility operating a-Si:H TFT at higher temperatures.  The TFT used in this study has a chromium gate, two layers of amorphous silicon nitride, two layers of amorphous silicon, and heavily doped n+ a-Si:H plus chromium on top to form the source and drain.  The first layer of amorphous silicon nitride (3500?) was deposited in PECVD at a higher rate, and the second at lower rate (500?).  Similarly the amorphous silicon deposition was divided into a lower deposition rate film (300?) near the channel, and a higher deposition rate film (1400?) on the top.  The bottom gate, inverted staggered TFT has a saturation regime mobility of 0.64 cm2 V/sec, threshold voltage of 1.8 V, and subthreshold swing of 0.72 V/dec at room temperature.  The mobility improves to 1.01 cm2 V/sec, threshold voltage to 1.25 V at 80ºC.  Even though the transistor’s electrical performance improves as temperature rises, its electrical stability suffers as well.  We investigated the threshold voltage shift of TFT at elevated temperature of 80ºC to evaluate the trade-off between electrical performance and stability.  Since we expect an increase in threshold voltage shift at higher temperature we also studied devices at different operation regimes to search for the most stable biasing conditions for a-Si:H TFT.

We find that, regardless of the current level, the most stable regime of operation is the saturation regime, where VDS=VGS.  For example with 500nA of stress current, the transistor biased in the linear regime (VGS>VDS) has a ΔVT of almost 6V after 10000sec, where the TFT biased in saturation only experienced a ΔVT of only 1V.  In general, there is a factor of at least four in reduction of the threshold voltage shift when we operate a TFT in the saturation regime versus the linear regime.  We attribute the discrepancy on the gate-induced electric field in the gate insulator.  Two identical TFT’s can suffer different threshold voltage shift while driving the same current, if the gate-to-drain electric fields are different.  In the case where VGS>VDS, a large fraction of the gate insulator experiences a high electric field due the gate; gate field accelerates electrons into the gate insulator and causes the formation of trapped charges near the a-Si:H / a-SiNX:H interface.  On the contrary, same TFT undergoing current-temperature-stress (CTS) with the gate and drain shorted together shows much smaller electrical degradation, even if the stress currents are identical.  This is due to a reduction of the electric field in the gate insulator by biasing the gate and drain at the same potential.  Under this condition, only electrons close to the source get accelerated and injected into the gate insulator.  Moreover since the a-Si:H TFT is operating in the saturation regime during the electrical stress, a lower gate bias is needed to achieve the same current as the TFT operating in the linear regime.  We believe that it is possible to operate a-Si:H TFT above room temperature, as long as we choose the right biasing scheme to minimize threshold voltage shift.  Nevertheless, a high temperature operation still degrades device at much higher rate and we recommend operating a-Si:H TFT at lower temperatures if possible.

This work was done in collaboration and was partially financially supported by Applied Komatsu Technology America. 

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